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  1. Multi-objective genetic optimized multiprocessor SoC design
Multi-objective genetic optimized multiprocessor SoC design
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Multi-objective genetic optimized multiprocessor SoC design

Arjomand, M.

  1. DOI:10.1109/ISSOC.2008.4694887
  2. Main Entry: Arjomand, M.
  3. Title:Multi-objective genetic optimized multiprocessor SoC design.
  4. Publisher:2008.
  5. Abstract:In this paper, we introduce a new Multi-Objective Genetic Algorithm (MOGA) for mapping a given set of intellectual property onto a Network-on-Chip architecture such that for a specific application total communication cost and energy consumption become optimized while bandwidth constraints are satisfied. As the main theoretical contribution, we first introduce a generic queuing model to estimate performance and an experimental energy consumption model during the design phase, with acceptable accuracy. Then, an efficient genetic algorithm employs these models to propose a Pareto optimal front for an application and an arbitrary topology. Experimental results show that the proposed algorithm is very fast which results in a new approach for mapping MPSoC cores on chip. © 2008 IEEE
  6. Notes:Sharif Repository
  7. Subject:Arbitrary topology.
  8. Subject:Bandwidth constraint.
  9. Subject:Communication cost.
  10. Subject:Design phase.
  11. Subject:Efficient genetic algorithms.
  12. Subject:Energy consumption.
  13. Subject:Energy consumption model.
  14. Subject:Multi objective.
  15. Subject:Multi-objective genetic algorithm.
  16. Subject:Multi-processor SoC.
  17. Subject:Network-on-chip architectures.
  18. Subject:New approaches.
  19. Subject:On chips.
  20. Subject:Pareto-optimal front.
  21. Subject:Queuing models.
  22. Subject:Application specific integrated circuits.
  23. Subject:Electric network topology.
  24. Subject:Microprocessor chips.
  25. Subject:Multiobjective optimization.
  26. Subject:Programmable logic controllers.
  27. Subject:Telecommunication systems.
  28. Subject:Electric load forecasting.
  29. Added Entry:Sarbazi Azad, H.
  30. Added Entry:Amiri, S. H.
  31. Added Entry:Sharif University of Technology.
  32. Source: 2008 International Symposium on System-on-Chip, SOC 2008, Tampere, 5 November 2008 through 6 November 2008 ; December , 2008 ; 9781424425419 (ISBN)
  33. Web Site:https://ieeexplore.ieee.org/document/4694887

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